As for an image display apparatus for displaying an image by means of a video signal, a liquid crystal panel including pixels placed like a lattice and the like are known. The kind of image display apparatus is connected to a video signal source such as a personal computer (hereinafter, abbreviated as a PC) or a workstation server so that it can display an image based on a video signal supplied from the video signal source.
The image display apparatus is supplied with a video signal which has a higher frequency than a horizontal synchronizing signal indicating a horizontal display period of a display image and which changes a signal level in synchronization with a clock including a certain frequency (hereinafter, referred to as a dot clock). The image display apparatus regenerates the dot clock that has the same frequency as the dot clock used by the video signal source, and displays the image based on the video signal supplied from the video signal source by using the regenerative dot clock. In this specification, the dot clock regenerated by the image display apparatus is called a regenerative dot clock. The image display apparatus includes a PLL (Phase Locked Loop) circuit, changes the frequency dividing ratio of a frequency divider provided to the PLL circuit and thereby adjusts the frequency of the regenerative dot clock so as to be an integral multiple of the horizontal synchronizing signal of the video signal supplied from the video signal source.
In the case where the frequency (or frequency dividing ratio) of the dot clock used by the video signal source is known, it is possible, by accordingly setting the frequency dividing, ratio of the PLL circuit, to correctly match the frequency of the regenerative dot clock with the dot dock used by the video signal source.
In the case where an inputted video signal, is an analog signal, however, there is no information on the dot clock supplied from the video signal source to the image display apparatus, and the horizontal synchronizing signal and a vertical synchronizing signal are supplied as timing information. In this case, the image display apparatus cannot obtain the information on a dot clock frequency (or frequency dividing ratio) used by the video signal source in advance. Therefore, there is no guarantee that the frequency dividing ratio of the PLL circuit can be correctly set. Unless the frequency dividing ratio is correctly set, the frequency of the regenerative dot dock will not match the frequency of the dot clock used by the video signal source. Therefore, there arises a deviation between the regenerative dot clock for capturing the video signal and the video signal so that the image can no longer be correctly displayed.
It is also possible for a user of the image display apparatus to adjust the frequency of the regenerative dot clock while viewing the display image by using an adjustment function provided to the image display apparatus in advance. However, such manual frequency adjustment of the regenerative dot clock is very cumbersome for the user.
Thus, there are proposals of various techniques for automatically adjusting the frequency of the regenerative dot clock.
For instance, Japanese patent No. 3487119 describes a dot clock regenerating apparatus including an A/D converter for converting a video signal (analog) inputted from the video signal source to a digital signal, a PLL circuit for generating a sampling clock (regenerative dot clock) synchronized with the horizontal synchronizing signal of the video signal, frequency analyzing means for detecting a folded frequency component generated when performing A/D conversion with a regenerative dot clock including a different frequency than the dot clock used by the video signal source, and a frequency dividing ratio setting circuit for adjusting the frequency dividing ratio of the PLL circuit according to the folded frequency component detected by the frequency analyzing means.
The dot clock regenerating apparatus matches the dot clock used by the video signal source with the regenerative dot clock by automatically adjusting the frequency of the regenerative dot clock to minimize the folded frequency component. Therefore, manual frequency adjustment is not necessary.
As for another method of automatically adjusting the frequency of the regenerative dot clock, the technique disclosed in U.S. Pat. No. 5,767,916 is known.
The technique described in U.S. Pat. No. 5,767,916 first measures the frequency of the horizontal synchronizing signal supplied together with an analog video signal (RGB) and counts the number of lines per frame. Subsequently, it estimates horizontal resolution of the analog video signal and the frequency of the dot clock with reference to a table created in advance based on the frequency and the number of lines of the horizontal synchronizing signal so as to provisionally set a horizontal display width E of the analog video signal and a frequency dividing ratio n. Next; it acquires a horizontal display width W of an actually captured video signal. Here, if W<E or W>E, a new frequency dividing ratio n′ is acquired by [n′=n×E/W], and the same adjustment is made in the next frame. If W=E, it determines that the frequency of the regenerative dot clock has been correctly adjusted, and finishes the automatic adjustment.
In recent years, there are a variety of video signals, and the video signals in various formats are inputted to the image display apparatus. As for the video signals representing those, there are XGA (eXtended Graphics Array), SXGA (Super XGA) and the like which are the VESA (Video Electronics Standards Association) standards. As demand for wide size screens has grown due to spread of a digital high definition image products, there is also a signal in a WXGA (Wide XGA: 1280×768) format that extends the horizontal width of the XGA.
As mentioned above, the image display apparatus is supplied with the horizontal synchronizing signal and the vertical synchronizing signal other than the video signal. Therefore, it is difficult to correctly determine the format of the inputted video signal just by using such synchronizing signal information.
The image display apparatus includes a frame memory for storing the video signals per screen. However, memory capacity of the frame memory is limited due to costs and the like. Therefore, there are the cases where there is a difference between the number of horizontal video data capturable by the frame memory (hereinafter, referred to as capture width) and the horizontal display width which is the number of horizontal video data as a display subject.
In the case where the horizontal display width is larger than the capture width of the frame memory, the horizontal display width is normally matched with the capture width of the frame memory by reducing the number of analog signals that are sampled when using an A/D converter to convert the analog video signal. In the case where the horizontal display width is smaller than the capture width of the frame memory, the horizontal display width is matched with the capture width of the frame memory by increasing the number of analog signals that are sampled when using an A/D converter to convert the analog video signal. As A/D conversion is performed by using the regenerative dot clock generated from the horizontal synchronizing signal, it is necessary to adjust the frequency of the regenerative dot clock so that the horizontal display width matches the capture width of the frame memory.
Furthermore, in conjunction with higher resolution of the video signal in recent years, there are the cases where the frequency of the regenerative dot clock exceeds the maximum operating frequency operable in the A/D converter and in the video processing unit for executing a process for displaying the video signal on a display or the like. In this case, it is necessary to make an adjustment so that the frequency of the regenerative dot clock does not exceed the maximum operating frequency by reducing the capture width of the video data of the frame memory.
As mentioned above, however, it is difficult to correctly determine the format of the video signal. And there is no guarantee that the frequency dividing ratio of the PLL circuit for generating the regenerative dot clock can be correctly set according to the format of the video signal and the capture width of the frame memory. For that reason, the frequency of the regenerative dot clock for capturing the video signal deviates from the frequency of the video signal so that the image can no longer be correctly displayed.